1. Field of the Invention
The present invention relates to a sampling phase control apparatus for use in a transmission system on a digital subscriber loop system.
2. Description of the Related Art
Generally, in a transmission system for use in a digital subscriber loop, a discriminating circuit for discriminating a sign of a received signal and an equalizer for removing an intersymbol interference component from the received signal are provided. On the other hand, a sampling phase control circuit is provided to control a phase of a baud rate clock signal supplied to the entire system including the equalizer.
In the above-mentioned system, a training period is provided as a set-up mode to establish a communication state such as a total duplex communication state. The set-up mode is classified into a cold start mode where the system is started from a fully-reset state and a warm start mode where the system is started from a subscriber line holding state. According to the American National Standards Institude (ANSI) standards, the training period for the cold start mode is prescribed to be within 15 s and the training period for the warm start mode is prescribed within 300 ms.
During the training period, the coefficients of an FIR filter of the equalizer and the like are converged and the phase of the phase sampling control circuit is captured (converged). However, the convergence of the equalizer and the like interferes with the capture of the phase of the sampling phase control circuit, thus prolonging the training period.
In a first prior art sampling phase control circuit, intersymbol interference components of received signals are accumulated, and the phase of the clock signal is advanced or retarded in accordance with the accumulated intersymbol interference components (see Y. Takahashi et al., "An ISDN Echo-Cancelling Tranceiver Chip Set for 2BIQ Coded U-Interface", IEEE Journal of Solid State Circuits Vol. 24, No. 6, Nov. 1989). In the first prior art sampling phase control circuit, however, the control speed of the phase of the clock signal is very low. As a result, the capture of the phase of the clock signal is delayed, and accordingly, the convergence of the equalizer and the like is delayed. Particularly, the prescribed training period for the warm start mode may not be satisfied. This will be explained later in detail.
In a second prior art sampling phase control circuit, intersymbol interference components of received signals are accumulated, and a differential value of the accumulated intersymbol interference components is calculated. Then, the phase of the clock signal is advanced or retarded in accordance with the accumulated intersymbol interference components and their differential values (see T. Ito et al., "A Fast Convergence Method for a Decision Feedback Equalizer Based on a Variable-Step Phase Control", IEICE Journal B-572, pp. 3-238, 1992). In the second prior art sampling phase control circuit, however, the control speed of the phase of the clock signal is very high. As a result, even after the equalizer and the like are converged, the phase of the clock signal has jitter.